1. Field of the Invention
The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to techniques for generating memory efficient technology libraries used for timing and power estimations.
2. Related Art
An electronic design automation (EDA) system is a computer software system used for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this high level design language description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. The generic netlist can be translated into a lower level technology-specific netlist based on a technology-specific library that has gate-specific models for timing and power estimation. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. A single node can have multiple fan-ins and multiple fan-outs. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. One result is a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
The design flow for the design of integrated circuits (e.g., ASIC, microprocessors, microcontrollers, etc.) requires several descriptions of the design library that are used as input to different CAD tools. For instance, a synthesis library is typically required. The main loop in the IC design environment consists of describing the IC design in terms of primitive models from the synthesis library, verifying (e.g., functionality, power and timing constraints, etc.) through various verification techniques and then refining and correcting the IC design. During this process, timing and power estimations or ("simulations") are often performed by the computer system to optimize the IC design and to determine if the overall circuit design is maintaining prescribed timing and power constraints.
FIG. 1 illustrates an example library cell 10. Within a technology library, each signal path of a library cell 10 can have its own timing model. For instance, for cell 10, a first path from input 12 to output 30 can ha ve one timing model while a second path from input 16 to output 30 can have a second timing model. The timing delay (or other constraint) through a path from one input to an output is called a timing arc. Library cell 10 has at least four timing arcs. A timing arc is modeled based on a function of two variables, usually the input transition rate and the output capacitance load. Originally, timing models for timing arcs were based on fixed-form linear equations of output capacitance load. Later, these timing models (e.g., for generic CMOS) were based on a linear equation including both of these two input variables (with fixed coefficients) and, similarly, the same linear equation form was used to model all of the gates of a given technology library. Although the linear equation form was the same for all gates, the coefficients of the linear equation could change from timing arc to timing arc within the same technology library. This allowed the timing calculations to be generalized across the entire technology library and thereby made the timing calculations easier to perform. However, the calculations were not entirely accurate because some library gates were not well modeled by the fixed-form linear equation. It is desired to provide a more accurate method for providing timing delay estimations within an EDA system.
To improve accuracy, piecewise linear analysis was introduced to simulation and this provided a linear representation in each region but used a two dimensional representation. Three dimensional (3-D) non-linear look-up tables were then introduced that used bilinear equations for interpolation within the data points of the table. Using this prior art modeling method, each timing arc of a technology library is represented by a separate look-up table. Each point of a look-up table is referenced by an input transition rate and an output capacitance load and represents a delay value. Interpolation and extrapolation functions are used to determine values in between the given data points. FIG. 2A illustrates an original look-up table provided by the user. FIG. 2B illustrates the interpolated results of FIG. 2A showing the accuracy of a look-up table approach particularly for tables with "abnormal" data, such as the data at the upper right comer of FIG. 2A.
Although look-up tables, like the ones shown in FIG. 2A and FIG. 2B, provide very accurate timing and power simulations, they unfortunately also consume relatively large amounts of memory resources within an EDA system as one technology library can contain as many as tens of thousands of look-up tables. For instance, each timing arc of each library cell can require its own individual look-up table data structure. Assuming each look-up table is 5.times.5 (e.g., consuming about 1.0 K bytes each) and assuming further that some technology libraries have over 1,000 cells per library, there can be between 5,000 and 20,000 look-up tables per technology library. Because multiple timing arcs can exist within each library cell, a single cell can require as much as 5-20 K bytes of memory storage for look-up tables. At this number, between 5.0 M bytes and 20.0 M bytes of memory can be required to provide delay data for a typical technology library. Further, large look-up table sizes slow down timing calculations. Because technology libraries are approaching 2,000 cells and further because users demand that design tools be able to deal with multiple different operating conditions (each of which requires a different set of timing data), it is desired to provide a more memory efficient method for providing timing delay estimations within an EDA system.
Accordingly, what is needed is a system and method for modeling the timing and/or the power for cells of a netlist that is memory efficient. Furthermore, what is needed is a system and method for accurately modeling the timing and/or power of cells of a netlist. In view of the above needs, the present invention provides a system and method for increasing the efficiency of an IC design process to thereby provide a faster, more cost effective and more accurate IC design process. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.